package spinal_loongarch_core132

import spinal.core._
import spinal.lib._

class CoreIn extends Bundle{
    val id    = UInt(9 bits)
    val intr  = UInt(8 bits)
    val ipi   = Bool()
    def setEmpty():Unit = {
        id   := U(0)
        intr := U(0)
        ipi  := False
    }
}

class CoreTop extends Component{
    val io = new Bundle{
        val core = in(new CoreIn)
        val axi  = master(new LabAxi3)
        val debug_wb:CoreDebug = out(new CoreDebug)
    }
    val s_fe1 = new StageFe1
    val s_fe2 = new StageFe2
    val s_de  = new StageDe
    val s_ex1 = new StageEx1
    val s_ex2 = new StageEx2
    val s_ex3 = new StageEx3
    val s_wb  = new StageWb
    val csr_file = new CsrFile
    val reg_file = new RegFile(2)
    val div = new Dividor(32)
    val tlb = new Tlb
    val icache = new ICache
    val dcache = new DCache
    val arbiter = new LabAxi3Arbiter

    arbiter.io.axi <> io.axi
    icache.io.imiss <> arbiter.io.imiss
    dcache.io.dmiss <> arbiter.io.dmiss

    icache.io.isrch <> tlb.io.isrch
    dcache.io.dsrch <> tlb.io.dsrch

    dcache.io.icop <> icache.io.icop

    s_fe1.io.ireq  <> icache.io.ireq
    s_fe2.io.iresp <> icache.io.iresp
    s_fe2.io.iexcpt:= icache.io.iexcpt

    s_de.io.r     <> reg_file.io.r

    s_ex1.io.tlbrw  <> tlb.io.rw
    s_ex1.io.invtlb <> tlb.io.inv

    s_ex1.io.dreq  <> dcache.io.dreq
    s_ex2.io.dexcpt:= dcache.io.dexcpt
    s_ex3.io.dresp <> dcache.io.dresp

    s_ex1.io.div   <> div.io.i
    s_ex3.io.div   <> div.io.o

    s_wb .io.grw   <> reg_file.io.w

    s_fe1.io.brbus <> s_ex1.io.brbus
    s_fe2.io.brbus <> s_ex1.io.brbus
    s_de .io.brbus <> s_ex1.io.brbus

    s_fe1.io.exbus <> csr_file.io.exbus
    s_fe2.io.exbus <> csr_file.io.exbus
    s_de .io.exbus <> csr_file.io.exbus
    s_ex1.io.exbus <> csr_file.io.exbus
    s_ex2.io.exbus <> csr_file.io.exbus
    s_ex3.io.exbus <> csr_file.io.exbus

    s_de .io.fw(0) := s_ex1.io.fw
    s_de .io.fw(1) := s_ex2.io.fw
    s_de .io.fw(2) := s_ex3.io.fw
    s_de .io.fw(3) := s_wb .io.fw

    s_fe1.io.oc   <> s_fe2.io.ic
    s_fe1.io.odat <> s_fe2.io.idat
    s_fe2.io.oc   <> s_de .io.ic
    s_fe2.io.odat <> s_de .io.idat
    s_de .io.oc   <> s_ex1.io.ic
    s_de .io.odat <> s_ex1.io.idat
    s_ex1.io.oc   <> s_ex2.io.ic
    s_ex1.io.odat <> s_ex2.io.idat
    s_ex2.io.oc   <> s_ex3.io.ic
    s_ex2.io.odat <> s_ex3.io.idat
    s_ex3.io.oc   <> s_wb .io.ic
    s_ex3.io.odat <> s_wb .io.idat

    csr_file.io.wb <> s_wb.io.tocsr
    
    csr_file.io.core  <> io.core
    csr_file.io.totlb <> tlb.io.csr
    csr_file.io.tofe  <> s_fe1.io.csr
    csr_file.io.tode  <> s_de.io.csr
    csr_file.io.toex  <> s_ex1.io.csr
    csr_file.io.rw    <> s_ex1.io.csrrw

    csr_file.io.tlbrd   <> tlb.io.rd
    csr_file.io.tlbsrch <> tlb.io.srch

    s_wb.io.debug <> io.debug_wb
}
